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This is the final tutorial in the series of tutorials on the Single Port SRAM design, and is the final step in the full circuit analysis that was done by a design engineer before the design was built in the fab. There are many subtleties to be considered when running full circuit simulations on memories with the main goal of analyzing the weakest portions of the design and evaluating how much margin there is under worst case situations. Combinations of cycles must be considered to determine how a previous cycle can affect the quality of the next cycle. Location of the memory cell accessed in the old and new cycle, old data vs. new data, write cycle effects on the next read cycle are all evaluated in this tutorial. Results of SPICE simulations and waveforms will be presented along with discussion of the top level simulation schematic that must accurately model the loading by all cells on signal nodes in the layout.
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This tutorial follows the read path from the word line to the input of the sense amp which includes the initial column decode that selects the appropriate bit line. Particular attention will be paid to the large capacitive load that the memory cells have on the bit lines, and waveforms from simulat…
The sub-blocks of the dual port memory architecture is presented in the tutorial with a key focus on the path from the array bit lines to the data pins for both the read and write. A memory can have many possibilities of how the bits and bits per word is configured which is based on the number of r…
The interaction in the array between the two ports can have some adverse effects that must be evaluated when designing a Dual Port SRAM, especially when one of the ports is doing a write. This tutorial takes a close look at a "Word Line collision" that occurs when one port is writing while the othe…
This dual port SRAM utilizes a 2-sided differential sensing scheme by taking advantage of the fact that both bit true and bit complement bit lines are available due to the nature of the 6T SRAM bit cell. The sense amp is clocked by a 1 of 4 decoded Sense Amp Clock utilizing a regenerative feedback …
A synchronous RAM is activated on the rising edge of clock and basically has 2 main internal cycles: the active cycle when the read or write is occurring and the pre-charge cycle that sets up the initial conditions for the next new clock cycle. The timing requirements and relationships that the cus…
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