ABOUT THIS EPISODE
A synchronous RAM is activated on the rising edge of clock and basically has 2 main internal cycles: the active cycle when the read or write is occurring and the pre-charge cycle that sets up the initial conditions for the next new clock cycle. The timing requirements and relationships that the customer must meet will first be reviewed with a specific focus on the clock cycle. The key internal signals of the word line and the pre-charging of the bit lines and their relationship will be discussed along with the pre-charge circuitry. The timing interaction and relationships between the 2 ports must be kept in mind.
English
United States
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OTHER EPISODES IN THIS PODCAST
This tutorial follows the read path from the word line to the input of the sense amp which includes the initial column decode that selects the appropriate bit line. Particular attention will be paid to the large capacitive load that the memory cells have on the bit lines, and waveforms from simulat…
The sub-blocks of the dual port memory architecture is presented in the tutorial with a key focus on the path from the array bit lines to the data pins for both the read and write. A memory can have many possibilities of how the bits and bits per word is configured which is based on the number of r…
This dual port SRAM utilizes a 2-sided differential sensing scheme by taking advantage of the fact that both bit true and bit complement bit lines are available due to the nature of the 6T SRAM bit cell. The sense amp is clocked by a 1 of 4 decoded Sense Amp Clock utilizing a regenerative feedback …
The interaction in the array between the two ports can have some adverse effects that must be evaluated when designing a Dual Port SRAM, especially when one of the ports is doing a write. This tutorial takes a close look at a "Word Line collision" that occurs when one port is writing while the othe…
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