이 에피소드에 관해
I first spoke to Chipletti cofounders Kauser Johar and Catriona Wright in The BritChips Podcast ‘Chipletti’s Big Stack’ in June last year. Chipletti, you may recall, was one of the startups selected to participate in the third cohort of the government-sponsored ChipStart incubator, managed by Silicon Catalyst UK.
At that time they were hard at work developing high-speed cache memory chiplets (the clue is in the company name) designed to stack on top of logic chips so you get more cache memory without needing extra space on the silicon.
But that’s all changed as you’ll hear (and see) in this latest episode of The BritChips Podcast, in which they explore the latest developments in edge AI hardware, focusing on innovative memory stacking, chiplet integration, and simulation tools that are revolutionizing the design and deployment of AI inference systems at the edge, aka Physical AI.
In this episode:
* The progression from cache memory optimization to edge AI applications
* Challenges and solutions in 3D memory stacking for low-power devices
* Designing chiplets for AI inference in mobile and real-time applications
* The role of simulators in predicting hardware performance before silicon fabrication
* Milestones: FPGA prototyping, chiplet integration, and silicon manufacturing timelines
* The strategic focus on supply chain sovereignty and local manufacturing for AI hardware
* How this integrated approach uniquely positions the company within a competitive market
Topics:
* Introduction to the evolution from cache memory to edge AI inference hardware
* Detailed benchmarking results on memory stacking performance improvements
* Bridging cache memory work with new edge AI chip architectures
* Exploring applications suitable for 10-15 watt power envelopes, including drones and robots
* Real-time AI inference and the importance of latency in safety-critical systems
* GPU limitations in real-time environments and architecture optimization for edge AI
* Designing chips that are more resilient, reliable, and power-efficient for edge AI use
* Transition from memory chiplet design to integrated compute chiplets
* The move from selling memory chiplets to providing complete system modules
* Development of a high-fidelity simulator for hardware performance prediction
* Creating the simulator with internal expertise and academic collaboration
* Engaging potential customers and enabling early deployment through simulation
* Making the simulator accessible to developers early in the hardware development cycle
* How the simulator models future technology and non-existent hardware
* The abstraction level and accuracy of the simulation models
* Using simulation to inform design decisions across multiple future hardware scenarios
* Customization and flexibility in the simulator for different hardware architectures
* Commercial use: Charged for simulation or a strategic tool?
* Milestones: FPGA prototypes, module integration, and upcoming silicon tape-outs
* Industry-standard FPGA development plans and timelines for demonstrations
* Funding strategies and milestone timelines, including venture capital and grants
The BritChips Podcast is proudly sponsored by Silicon Catalyst UK, Official Partner of the government-funded ChipStartUK semiconductor incubator.
This is a public episode. If you would like to discuss this with other subscribers or get access to bonus episodes, visit anttheantidote.substack.com
