このエピソードについて
A synchronous RAM is activated on the rising edge of clock and basically has 2 main internal cycles: the active cycle when the read or write is occurring and the pre-charge cycle that sets up the initial conditions for the next new clock cycle. The timing requirements and relationships that the customer must meet will first be reviewed with a specific focus on the clock cycle. The key internal signals of the word line and the pre-charging of the bit lines and their relationship will be discussed along with the pre-charge circuitry. The timing interaction and relationships between the 2 ports must be kept in mind.
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このポッドキャストの他のエピソード
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