TUNGKOL SA EPISODE NA ITO
What does it actually mean for connectivity IP to stop being a supporting function — and become the layer that determines whether a 3D IC delivers on its promise?
What you’ll learn...
(02:45) Archana's background: semiconductor IP, high-speed clocking, and AI memory subsystems
(03:49) Alphawave Semi's role in 3D IC — and why the interconnect layer is now foundational
(05:40) 3D IC integration headaches: signal integrity, power delivery, and thermal hotspots
(07:59) IP development for 3D ICs: co-optimizing with packaging, interposers, and photonics
(10:02) Friction points: methodology inertia, ecosystem immaturity, and standardization vs. customization
(12:26) Balancing performance, reliability, and manufacturability — and Alphawave Semi's validation approach
(14:51) The magic wand pick: open chiplet interoperability and solving thermal constraints
(17:27) What's accelerating now: UCIe adoption, cross-chain collaboration, photonics, and advanced packaging
More about this episode...
In this Season 3 premiere of the Siemens 3D IC Podcast, new host Tova Levy speaks with Archana Cheruliyil, Principal Product Marketing Manager at Alphawave Semi, a Qualcomm company, about what it really takes to develop IP for 3D ICs — and why connectivity has shifted from a background function to a system-defining one. Alphawave Semi's portfolio spans UCIe die-to-die interconnect, HBM memory interfaces, PCIe, CXL, and custom silicon, all optimized for the disaggregated architectures that 3D IC design demands.
Archana places connectivity IP at the center of the challenge: in stacked, chiplet-based designs, the interconnect layer directly determines system performance, power efficiency, and scalability. Signal integrity behaves differently in dense 3D electromagnetic environments, power delivery must be managed vertically across multiple dies, and thermal hotspots in stacked logic have no easy escape path — forcing teams into system-level trade-offs across signal, power, thermal, and packaging simultaneously. Adding photonics into the mix raises the stakes further, combining different materials and design constraints within the same package.
On the market side, Archana unpacks the tension between open standards like UCIe — which enable interoperability but can't always keep pace with customer demands — and the highly customized solutions that drive real differentiation. Siemens is highlighted as a key emulation and system-level validation partner, helping teams understand full-system behavior before silicon is produced.
The episode closes with Archana's vision for what would unlock the next phase of 3D IC adoption: a truly open chiplet marketplace that frees engineering cycles for innovation rather than integration reinvention — and progress on thermal management to enable deeper stacking across a broader range of applications.
Ideal for: 3D IC architects, silicon IP designers, advanced packaging engineers, chiplet ecosystem participants, EDA users, and anyone navigating the shift from monolithic SoC design to heterogeneous, disaggregated integration.
Connect with Tova Levy
Connect with Archana P Cheruliyil
