ACERCA DE ESTE EPISODIO
This course describes the state-of-the-art of tunable lasers, tunable laser technologies and control of tunable lasers. It also includes a brief introduction to the basics of semiconductor lasers, as well as background on DFB lasers, in particular how a grating works as a wavelength selective element in DFB and DBR lasers. Tuning mechanisms and tuning properties will be described, and the operation of modified structures with extended tuning range will be explained, including sampled gratings and super structure gratings. The properties of codirectional couplers and the use of these in tunable lasers will be discussed. Devices such as external cavity lasers, wavelength selectable lasers, and tunable VCSELs, will also be described. Throughout the course numerous examples of laser structures from the recent technical literature will be presented. Practical issues such as characterization, operation, and control of tunable lasers, as well as switching speed and reliability, will be included.
Inglés
Estados Unidos
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OTROS EPISODIOS EN ESTE PODCAST
A synchronous RAM is activated on the rising edge of clock and basically has 2 main internal cycles: the active cycle when the read or write is occurring and the pre-charge cycle that sets up the initial conditions for the next new clock cycle. The timing requirements and relationships that the cus…
This tutorial follows the read path from the word line to the input of the sense amp which includes the initial column decode that selects the appropriate bit line. Particular attention will be paid to the large capacitive load that the memory cells have on the bit lines, and waveforms from simulat…
This dual port SRAM utilizes a 2-sided differential sensing scheme by taking advantage of the fact that both bit true and bit complement bit lines are available due to the nature of the 6T SRAM bit cell. The sense amp is clocked by a 1 of 4 decoded Sense Amp Clock utilizing a regenerative feedback …
The sub-blocks of the dual port memory architecture is presented in the tutorial with a key focus on the path from the array bit lines to the data pins for both the read and write. A memory can have many possibilities of how the bits and bits per word is configured which is based on the number of r…
The interaction in the array between the two ports can have some adverse effects that must be evaluated when designing a Dual Port SRAM, especially when one of the ports is doing a write. This tutorial takes a close look at a "Word Line collision" that occurs when one port is writing while the othe…
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